Fast fourier transformer

ABSTRACT

A fast Fourier transformer (FFT) includes a radix-2 butterfly unit configured to perform a butterfly operation on input data; a buffer unit configured to buffer data outputted from the radix-2 butterfly unit and output the buffered data to the radix-2 butterfly unit; a multiplexing unit configured to selectively output a twiddle factor; and a constant multiplier configured to multiply the data outputted from the radix-2 butterfly unit by the twiddle factor outputted from the multiplexing unit.

CROSS-REFERENCES TO RELATED APPLICATIONS

The present application claims priority under 35 U.S.C. 119(a) to KoreanApplication No. 10-2010-0134061, filed on Dec. 23, 2010 in the Koreanintellectual property Office, which is incorporated herein by referencein its entirety set forth in full.

BACKGROUND

Exemplary embodiments of the present invention relate to a fast Fouriertransformer (FFT), and more particularly, to an FFT which is widely usedin a signal processing field such as an orthogonal frequency divisionmultiplexing (OFDM) modulation and demodulation communication system.

An FFT is widely used in a signal processing field such as an OFDMmodulation and demodulation communication system.

Such an FFT is a component which is essentially used in an OFDMreceiver. As the length of the FFT increases, the calculation thereofbecomes very complicated. Accordingly, a variety of design methods forovercoming such a problem have been proposed.

In general, a method of designing an FFT is divided into an in-placemethod and a pipelined method.

In the in-place method, a single memory having an address sizecorresponding to the length of the FFT is provided, and data is read ata specific address, subjected to a radix-r operation, and then stored ina memory space having the same address.

In the in-place method, since a single radix-r unit is used, the entireoperation time increases with the length of the FFT and the number ofstages. However, since the single radix-r unit is used, the in-placemethod has an advantage in terms of the circuit size.

In the pipelined method, the architecture of the FFT includes aplurality of stages which are coupled in series to each other. Each ofthe stages has its own radix-r unit and separately includes a buffer forstoring data.

Therefore, since the respective stages operate independently, aplurality of radix-r operations may be performed at the same time.Therefore, while the memory is used at the same level as the in-placedesign method, the pipeline design method exhibits much higherthroughput than in the in-place design method, because the respectivestages may perform radix-r operations at the same time.

The above-described technical configuration is a related art for helpingan understanding of the present invention, and does not indicate a priorart which is widely known in the technical field to which the presentinvention pertains.

SUMMARY

An embodiment of the present invention relates to an FFT which minimizesthe number of complex multipliers used for designing an FFT in apipelined method and optimizes the number of multipliers, therebyreducing a circuit size and power consumption.

In one embodiment, an FFT includes a radix-2 butterfly unit configuredto perform a butterfly operation on input data; a buffer unit configuredto buffer data outputted from the radix-2 butterfly unit and output thebuffered data to the radix-2 butterfly unit; a multiplexing unitconfigured to selectively output a twiddle factor; and a constantmultiplier configured to multiply the data outputted from the radix-2butterfly unit by the twiddle factor outputted from the multiplexingunit.

The FFT may further include a radix-2⁵ butterfly processor in which theradix-2 butterfly unit, the buffer unit, the multiplexing unit, and theconstant multiplier are configured as one stage.

The FFT may further include a radix-2^(m) butterfly processor in whichthe radix-2 butterfly unit, the buffer unit, the multiplexing unit, andthe constant multiplier are configured as one stage.

The twiddle factor may be induced according to a division method basedon a common factor algorithm in a discrete Fourier transform (DFT)formula.

The buffer unit may perform buffering as much as the butterfly operationtime of the radix-2.

In another embodiment, an FFT includes a radix-2⁵ butterfly processorconfigured to perform a butterfly operation on input data; a memory unitconfigured to store data outputted from the radix-2⁵ butterfly processorand output the buffered data to the radix-2⁵ butterfly processor; atwiddle ROM configured to store a twiddle factor; and a multiplierconfigured to multiply the data outputted from the radix-2⁵ butterflyprocessor by the twiddle factor outputted from the twiddle ROM.

The radix-2⁵ butterfly processor, the memory unit, the twiddle ROM, andthe multiplier may be connected in a pipelined method.

The twiddle factor may be induced according to a division method basedon a common factor algorithm in a DFT formula.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects, features and other advantages will be moreclearly understood from the following detailed description taken inconjunction with the accompanying drawings, in which:

FIG. 1 is a diagram explaining the configuration of an FFT usingradix-2⁵ in accordance with an embodiment of the present invention

FIG. 2 is a diagram explaining a data flow of the FFT using radix-2⁵ inaccordance with the embodiment of the present invention; and

FIG. 3 is a diagram explaining the configuration of a 32K-point FFT inaccordance with an embodiment of the present invention.

DESCRIPTION OF SPECIFIC EMBODIMENTS

Hereinafter, embodiments of the present invention will be described withreference to accompanying drawings. However, the embodiments are forillustrative purposes only and are not intended to limit the scope ofthe invention.

The drawings are not necessarily to scale and in some instances,proportions may have been exaggerated in order to clearly illustratefeatures of the embodiments. Furthermore, terms to be described belowhave been defined by considering functions in embodiments of the presentinvention, and may be defined differently depending on a user oroperator's intention or practice. Therefore, the definitions of suchterms will be based on the descriptions of the entire presentspecification.

FIG. 1 is a diagram explaining the configuration of an FFT usingradix-2⁵ in accordance with an embodiment of the present invention. FIG.2 is a diagram explaining a data flow of the FFT using radix-2⁵ inaccordance with the embodiment of the present invention. FIG. 3 is adiagram explaining the configuration of a 32K-point FFT in accordancewith an embodiment of the present invention.

Referring to FIGS. 1 and 2, the FFT using radix-2⁵ in accordance withthe embodiment of the present invention includes a radix-2 butterflyunit 11, a buffer unit 12, a multiplexing unit 13, and a constantmultiplier 14.

The radix-2 butterfly unit 11 is configured to perform a butterflyoperation on input data x[n].

The buffer unit 12 is configured to buffer data outputted from theradix-2 butterfly unit 11 and output the buffered data to the radix-2butterfly unit 11.

The multiplexing unit 13 is configured to selectively output a twiddlefactor.

The constant multiplier 14 is configured to multiply the data outputtedfrom the radix-2 butterfly unit 11 by the twiddle factor outputted fromthe multiplexing unit 13.

The radix-2 butterfly unit 11, the buffer unit 12, the multiplexing unit13, and the constant multiplier 14 form a radix-2⁵ butterfly processoras one stage.

Here, the twiddle factor is induced by a division method based on acommon factor algorithm in a discrete Fourier transform (DFT) formula.

A formula derivation process for designing the radix-2⁵ butterflyprocessor will be described as follows.

Equation 1 is a general DFT formula.

$\begin{matrix}{{{{X(k)} = {\sum\limits_{n = 0}^{N - 1}{{x(n)}W_{N}^{nk}}}},{k = 0},\ldots \mspace{14mu},{N - 1}}{{{where}\mspace{14mu} W_{N}^{nk}} = ^{\frac{{- {j2\pi}}\; {nk}}{N}}}} & \left\lbrack {{Equation}\mspace{14mu} 1} \right\rbrack\end{matrix}$

In order to divide this by radix-2⁵, a division method as expressed byEquation 2 below is used. In the division method, a variable n isdivided into n₁ to n₆, and a variable k is divided into k₁ to k₆according to a common factor algorithm.

$\begin{matrix}{{{n = {{\frac{N}{2}n_{1}} + {\frac{N}{4}n_{2}} + {\frac{N}{8}n_{3}} + {\frac{N}{16}n_{4}} + {\frac{N}{32}n_{5}} + n_{6}}}{{{where}\mspace{14mu} n_{1}} = \left\{ {0,1} \right\}}},{n_{2} = \left\{ {0,1} \right\}},{n_{3} = \left\{ {0,1} \right\}},{n_{4} = \left\{ {0,1} \right\}},{n_{5} = \left\{ {0,1} \right\}},{n_{6} = {{\left\{ {0,1,\ldots \mspace{14mu},{\frac{N}{32} - 1}} \right\} k} = {{k_{1} + {2k_{2}} + {4k_{3}} + {8k_{4}} + {16k_{5}} + {32k_{6}{where}\mspace{14mu} k_{1}}} = \left\{ {0,1} \right\}}}},{k_{2} = \left\{ {0,1} \right\}},{k_{3} = \left\{ {0,1} \right\}},{k_{4} = \left\{ {0,1} \right\}},{k_{5} = \left\{ {0,1} \right\}},{k_{6} = \left\{ {0,1,\ldots \mspace{14mu},{\frac{N}{32} - 1}} \right\}}} & \left\lbrack {{Equation}\mspace{14mu} 2} \right\rbrack\end{matrix}$

Equation 2 may be applied to Equation 1 to derive Equation 3 asexpressed below.

${X\left( {k_{1} + {2k_{2}} + {4k_{3}} + {8k_{4}} + {16k_{5}}\; + {32k_{6}}} \right)} = {\sum\limits_{n_{6} = 0}^{{N/32} - 1}{\sum\limits_{n_{5} = 0}^{1}{\sum\limits_{n_{4} = 0}^{1}{\overset{1}{\sum\limits_{n_{3} = 0}}{\sum\limits_{n_{2} = 0}^{1}{\sum\limits_{n_{1} = 0}^{1} {\quad {\quad{\quad{\quad {{\left\lbrack {x\begin{pmatrix}\begin{matrix}{{\frac{N}{2}n_{1}} + {\frac{N}{4}n_{2}} +} \\{{\frac{N}{8}n_{3}} + {\frac{N}{16}n_{4}} +}\end{matrix} \\{{\frac{N}{32}n_{5}} + n_{6}}\end{pmatrix}} \right\rbrack \cdot W_{N}^{{({{\frac{N}{2}n_{1}} + {\frac{N}{4}n_{2}} + {\frac{N}{8}n_{3}} + {\frac{N}{16}n_{4}} + {\frac{n}{32}n_{5}} + n_{6}})}{({k_{1} + {2k_{2}} + {4k_{3}} + {8k_{4}} + {16k_{5}} + {32k_{6}}})}}} = {{\sum\limits_{n_{6} = 0}^{{N/32} - 1}{\sum\limits_{n_{5} = 0}^{1}{\sum\limits_{n_{4} = 0}^{1}{\sum\limits_{n_{3} = 0}^{1}{\sum\limits_{n_{2} = 0}^{1}{\sum\limits_{n_{1} = 0}^{1}{{\left\lbrack {x\begin{pmatrix}\begin{matrix}{{\frac{N}{2}n_{1}} + {\frac{N}{4}n_{2}} +} \\{{\frac{N}{8}n_{3}} + {\frac{n}{16}n_{4}} +}\end{matrix} \\{{\frac{N}{32}n_{5}} + n_{6}}\end{pmatrix}} \right\rbrack \cdot W_{2}^{n_{1}k_{1}}}W_{4}^{n_{2}{({k_{1} + {2k_{2}}})}}W_{8}^{n_{3}{({k_{1} + {2k_{2}} + {4k_{3}}})}}W_{16}^{n_{4}{({k_{1} + {2k_{2}} + {4k_{3}} + {8k_{4}}})}}W_{32}^{n_{5}{({k_{1} + {2k_{2}} + {4k_{3}} + {8k_{4}} + {16k_{5}}})}}W_{N}^{n_{6}{({k_{1} + {2k_{2}} + {4k_{3}} + {8k_{4}} + {16k_{5}}})}}W_{N/32}^{n_{6}k_{6}}}}}}}}} = {{\sum\limits_{n_{6} = 0}^{{N/32} - 1}{\sum\limits_{n_{5} = 0}^{1}{\sum\limits_{n_{4} = 0}^{1}{\sum\limits_{n_{3} = 0}^{1}{\sum\limits_{n_{2} = 0}^{1}{\sum\limits_{n_{1} = 0}^{1}{x\begin{pmatrix}{{\frac{N}{2}n_{1}} + {\frac{N}{2}n_{2}} + {\frac{N}{8}n_{3}} +} \\{{\frac{N}{16}n_{4}} + {\frac{N}{32}n_{5}} + n_{6}}\end{pmatrix}}}}}}}} = {\sum\limits_{n_{6} = 0}^{{N/32} - 1}{\left\lbrack {\left\{ {\sum\limits_{n_{5} = 0}^{1}\begin{matrix}{\left\{ {\sum\limits_{n_{4} = 0}^{1}\begin{matrix}{\left\{ {\sum\limits_{n_{3} = 0}^{1}\begin{matrix}{\begin{Bmatrix}{\sum\limits_{n_{2} = 0}^{1}{\left\{ {\sum\limits_{n_{1} = 0}^{1}{{x\left( \begin{matrix}\begin{matrix}{{\frac{N}{2}n_{1}} + {\frac{N}{4}n_{2}} +} \\{{\frac{N}{8}n_{3}} + {\frac{N}{16}n_{4}} +}\end{matrix} \\{{\frac{N}{32}n_{5}} + n_{6}}\end{matrix} \right\}}W_{2}^{n_{1}k_{1}}}} \right\} \cdot}} \\{W_{4}^{n_{2}k_{1}}W_{2}^{n_{2}k_{2}}}\end{Bmatrix} \cdot} \\{W_{8}^{n_{3}{({k_{1} + {2k_{2}}})}}W_{2}^{n_{3}k_{3}}}\end{matrix}} \right\} \cdot} \\{W_{16}^{n_{4}{({k_{1} + {2k_{2}} + {4k_{3}}})}}W_{32}^{n_{5}{({k_{1} + {2k_{2}} + {4k_{3}}})}}W_{2}^{n_{4}k_{4}}}\end{matrix}} \right\} \cdot} \\{W_{4}^{n_{5}k_{4}}W_{2}^{n_{5}k_{5}}}\end{matrix}} \right\} \cdot} \right\rbrack {\quad{\cdot {\quad{W_{N}^{n_{6}{(\begin{matrix}{k_{1} + {2k_{2}} + {4k_{3}} +} \\{{8k_{4}} + {16k_{5}}}\end{matrix})}}W_{N/32}^{n_{6}k_{6}}}}}}}}}}}}}}}}}}}}}$

In Equation 3, butterfly units having a form of radix-2 may beconfigured from n₁ to n₅.

The twiddle factors applied to the respective stages may be expressed byn_(m) and k_(m).

When radix-2⁵ is derived according to Equation 3, it is possible toobtain an FFT flow as shown in FIG. 2.

Such a formula derivation process is used to form a variety ofradix-2^(m) butterfly processors.

That is, it is possible to form radix-2^(m) butterfly processors eachincluding the radix-2 butterfly unit 11, the buffer unit 12, themultiplexing unit 13, and the constant multiplier 14 as one stage.

FIG. 3 is a diagram explaining the configuration of a 32K-point FFT inaccordance with the embodiment of the present invention.

Referring to FIG. 3, the 32K-point FFT in accordance with the embodimentof the present invention includes a radix-2⁵ butterfly processor 1, amemory unit 4, a twiddle ROM 2, and a multiplier 3.

The radix-2⁵ butterfly processor 1 is configured to perform a butterflyoperation on input data through the radix-2 butterfly unit 11, as shownin FIGS. 1 and 2.

The memory unit 4 is configured to store data outputted from theradix-2⁵ butterfly processor 1, and the twiddle ROM 2 is configured tostore a twiddle factor.

The multiplier 3 is configured to multiply the data outputted from theradix-2⁵ butterfly processor 1 by the twiddle factor outputted from thetwiddle ROM 2.

The radix-2⁵ butterfly processor 1, the memory unit 4, the twiddle ROM2, and the multiplier 3 are connected in a pipelined method to form the32-K point FFT.

In accordance with the embodiment of the present invention, the numberof complex multipliers occupying a large portion of the circuit size inthe FFT may be minimized, and the number of multipliers may beoptimized. Therefore, it is possible to reduce the circuit size and thepower consumption.

Furthermore, when a modified radix-2⁵ butterfly processor and a generalradix-2⁵ butterfly processor are used together, it is possible tosupport a variety of FFT lengths while sharing hardware.

Furthermore, the formula derivation process proposed in the embodimentof the present invention may be used to configure a variety ofradix-2^(m) butterfly processors, and a hardware design method based onthe radix-2^(m) butterfly processors may be derived.

The embodiments of the present invention have been disclosed above forillustrative purposes. Those skilled in the art will appreciate thatvarious modifications, additions and substitutions are possible, withoutdeparting from the scope and spirit of the invention as disclosed in theaccompanying claims.

1. A fast Fourier transformer (FFT) comprising: a radix-2 butterfly unitconfigured to perform a butterfly operation on input data; a buffer unitconfigured to buffer data outputted from the radix-2 butterfly unit andoutput the buffered data to the radix-2 butterfly unit; a multiplexingunit configured to selectively output a twiddle factor; and a constantmultiplier configured to multiply the data outputted from the radix-2butterfly unit by the twiddle factor outputted from the multiplexingunit.
 2. The FFT of claim 1, further comprising a radix-2⁵ butterflyprocessor in which the radix-2 butterfly unit, the buffer unit, themultiplexing unit, and the constant multiplier are configured as onestage.
 3. The FFT of claim 1, further comprising a radix-2^(m) butterflyprocessor in which the radix-2 butterfly unit, the buffer unit, themultiplexing unit, and the constant multiplier are configured as onestage.
 4. The FFT of claim 3, wherein the twiddle factor is inducedaccording to a division method based on a common factor algorithm in adiscrete Fourier transform (DFT) formula.
 5. The FFT of claim 3, whereinthe buffer unit performs buffering as much as the butterfly operationtime of the radix-2 butterfly unit.
 6. An FFT comprising: a radix-2⁵butterfly processor configured to perform a butterfly operation on inputdata; a memory unit configured to store data outputted from the radix-2⁵butterfly processor and to output the buffered data to the radix-2⁵butterfly processor; a twiddle ROM configured to store a twiddle factor;and a multiplier configured to multiply the data outputted from theradix-2⁵ butterfly processor by the twiddle factor outputted from thetwiddle ROM.
 7. The FFT of claim 6, wherein the radix-2⁵ butterflyprocessor, the memory unit, the twiddle ROM, and the multiplier areconnected in a pipelined method.
 8. The FFT of claim 6, wherein thetwiddle factor is induced according to a division method based on acommon factor algorithm in a DFT formula.